1. Field of the Invention
This invention relates to the method of fabrication of printed circuit board (PCB) via structures that eliminate the need for presently used plated through holes (PTH) connection techniques on printed circuit boards.
2. Description of Background
In the present construction of printed circuit boards (PCB), when there is a need to translate from one signal plane to another, to connect similar power layers together, or to interconnect devices on the top or bottom surface of the PCB, a plated through hole (PTH) is created in the PCB. A PCB may also be referred to in the art as a card or board but for purposes of the present invention shall be considered to be the same. This PTH then performs the required interconnect function such as interconnecting reference planes to active circuits, or to interconnect signals between devices. With the speed of computer systems as well as the speeds for supporting circuitry now approaching transfer rates in excess of 10 gigabits/second and beyond, the effects of electrical stubs on the signal nets when a PTH is encountered can impact overall system performance severely. In most cases, as the density of the internal wiring of the PCB is increased, a designer may need to use multiple wiring layers to interconnect the signal traces due to space restrictions of available wiring planes. Thus the designer, when changing wiring planes, must use a translation via or a multiple number of translation vias on the PCB. These vias add an electrical parasitic stub on the wired net, which then impacts the overall electrical performance of the signal path. There have been several suggestions in the past for the elimination of via stubs. One method presently practiced to eliminate via stubs is to drill the via location to remove all unneeded metal from the via core. This requires significant rework of the PCB for critical applications which could prove to be costly when a significant number of locations are to be modified.
In the manufacture of a PCB, a normal PTH is constructed in a manner similar to the following process description. Referring to FIG. 1A, base core (100) materials such as double sided copper clad laminates are etched with the desired patterns on both copper surfaces. This is accomplished through photo resist and etch processes which are repeated for all other base cores (101-104) until all the required number of layers are formed. Then, the multiple cores (100 -104) are laminated together with pre-preg epoxies, forming a structure (10) composed of signal layers (13,14) between reference planes (12,15). Final connection to active and passive components is accomplished on the top (11) and bottom (16) surfaces. The structure (10) is then drilled (21) at the locations that require the formation of through holes (passing through the entire structure (10)) which may also be referred to hereafter as through vias or just vias. After several plating and subtractive processes are performed, the PTH (22) are formed that permit connections with wiring plane (50) at the predefined locations as seen in FIG. 1B.
In the design of large computer systems, PCB with a significant number of signal layers are possible. Multiple vias may be required to form a connection of internal wiring (50) between mounted circuit devices (30) or connections (40) to other interfaces such as I/O connectors.
For power distribution, interconnections of internal reference planes are made by vias and the power supply or ground returns are then connected by vias to the surface mounted circuitry. In addition, other components such as de-coupling capacitors and passive devices can be connected by vias to the reference planes. These two types of vias never need to be modified but on occasion need to be reworked to repair any failing via location due to cracking or failure that may occur within the via structure.
When circuits are interconnected, or when translation between internal wiring (50) and the external surfaces are required, a length of stub metal (60) is formed by the PTH (22) as shown in FIGS. 1B and 2A. The added length of stub metal (60) from the internal wiring plane (50) to the unused via end (23), creates an added capacitance and inductance which can cause a discontinuity on the net. To eliminate this stub metal (60) on very high speed nets, a hole (70) is drilled to a depth (71) just below the internal wiring plane (50) as seen in FIG. 2B. This drilling procedure requires significant control, setup and tolerance for the drilling such that the via is not over drilled.
Another problem as shown in FIG. 3A, is the stress failure of a connection between an internal wiring plane (50) (or reference plane (12,15), not shown in FIG. 3A) and the via structure associated with PTH (22). Very small cracks (200) are known to form between the plating of the through hole wall (66) and the internal wiring plane (50). When this happens, the board is rendered useless at that location. The present day method to repair this type of failure is to perform an engineering change. Both ends of the connection are removed from the internal wiring and a new discrete wire is soldered between the components. Another method that is used is to drill out the failed via and to solder a repair plug into the hole to reconnect the internal net.
A third problem with a PTH (22) as seen in FIG. 3B, is that the thickness (67) of the PTH wall (66) varies at different points along the PTH (22). The varying thickness (67) creates a problem with reliability and also requires a larger size via or multiple vias be used to supply current to the active devices. At present there are no plating methods that insure uniform thickness throughout the PTH (22).
A fourth problem is the creation of very fine PTH in technologies that are on the same level of nano technologies.
Various solutions have been proposed to manufacture vias and interconnects in PCB.                Among these are Hayes U.S. Pat. No. 5,377,902, Gruber et al. U.S. Pat. No. 6,461,136, Gruber et al. U.S. Pat. No. 6,708,873, Bourrieres et al. U.S. Pat. No. 6,783,797, Larson U.S. Pat. No. 6,982,191 and Curcio et al. U.S. Patent Application Publication US 2001/0027842, the disclosures of which are incorporated by reference herein.        